The functions implemented by this invention—the detection of local maxima and minima in an image—may be performed in different ways. One option is by means of general-purpose calculation digital systems. These systems may be programmed to process images, obtaining a result similar to that of the hardware proposed herein. To cite an example, a typical scenario might be the development of software for the analysis of images on a PC. This software would execute a series of instructions by means of the corresponding microprocessor until the desired result is achieved. The main advantage of this approach is the flexibility to undertake any type of task due to the generalistic nature of the underlying hardware. However, this advantage becomes a drawback when the specifications of a particular application require only a limited array of the functions provided by this type of system, but with a much lower power consumption and similar or even higher levels of performance, with regard to the number of operations per second. The non-specific nature of the hardware is precisely what prevents the fulfillment of said requirements on the majority of occasions. It is, however, possible to find a number of alternatives from the purely digital point of view, where the hardware may be progressively adjusted in order to obtain better performance parameters. Thus, we could consider the possibility of using digital signal processors optimised for the execution of certain operations which are useful for the processing of images, such as convolution, for example. Another option might be the implementation of processing primitives in reconfigurable integrated circuits such as FPGAs (Field-Programmable Gate Arrays) or CPLDs (Complex Programmable Logic Devices). As a last resort, digital circuitry specific for a particular application could be designed and integrated in a chip, thus obtaining the highest levels of performance and energetic efficiency.
The present invention falls beyond the context of exclusively digital implementation described above, and therefore differs in essence from any methodology based on the same. The fundamental difference lies in that, although in our case the basis is also the design of specific hardware for its integration in a chip, this hardware makes use of mixed signal circuitry, handling both analogue and digital signals. This characteristic enables the maximum exploitation of the physics of the transistors when processing the electrical signals representing the pixel values of an image, enabling the obtaining of better performance and power consumption values than an equivalent digital implementation. Many examples may be found reported in the literature concerning mixed signal circuitry for the processing of images [C. N. Stevenson, R. M. Lesperance, F. J. Schauerte and J. R. Troxell, “Image sensor method and apparatus having hardware implemented edge detection processing,” US Patent 2003/0108221 A1, Dec. 6, 2003; J. Dubois, D. Ginhac, M. Paindavoine, and B. Heyrman, “A 10000 FPS CMOS sensor with massively parallel image processing,” IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 706-717, 2008; P. Dudek, “SCAMP-3: A vision chip with SIMD current-mode analogue processor array,” Focal-plane Sensor-Processor Chips, published by Springer, 2011; J. Fernández Berni, R. Carmona Galán and Luis Carranza Gonzalez, “FLIP-Q: A QCIF resolution focal-plane array for low-power image processing,” IEEE J. Solid-State Circuits, vol. 46, no. 3, pp. 669-680, 2011].
The above examples are based on the processing architecture described in [Á. Rodriguez Vázquez, S. Espejo Meana and R. Dominguez Castro, “Programmable mixed-signal integrated circuit architecture for the production of autonomous vision systems in a single chip and/or pre-processing of images in higher-level systems,” Patent EP 1 580 814 (A1), Sep. 28, 2005]. This architecture is characterised by a two-dimensional array of interconnected elemental processors concurrently working together to perform a particular operation on an image.
The present invention is also supported by this processing hardware structure, as are other implementations [B. Amir and H. Saied, “Full CMOS minsum analog iterative decoders,” Patent US2005240647 (A1); L. A. Sánchez-Gaspariano, A. Diaz-Sánchez, G. Salda{umlaut over (n)}a-González, “High-precision current-based CMOS WTA/LTA filters,” Int. Conference on Electronics, Communications and Computers, 2007; M. Rahman, K. Baishnab, and F. Talukdar, “A high speed and high resolution VLSI winner-take-all circuit for neural networks and fuzzy systems,” Int. Symp. on Signals, Circuits and Systems, 2009; M. T. Moro-Frias, D. and Sanz-Pascual and C. A. de la Cruz Blas, “A novel current-mode winner-take-all topology,” European Conf. on Circuit Theory and Design, 2011, pp. 134-137; B. Tomatsopoulos and A. Demosthenous, “Low power, low complexity CMOS multiple-input replicating current comparators and WTA/LTA circuits,” European Conf. on Circuit Theory and Design, 2005, pp. 241-244; H. Hung-Yi, T. Kea-Tiong, T. Zen-Huan, and C. Hsin, “A low-power, high-resolution WTA utilizing translinear-loop pre-amplifier,” Int. Conf. on Neural Networks, 2010; R. Dlugosz and T. Talaska, “A low power current-mode binary-tree WTA/LTA circuit for Kohonen neural networks,” Int. Conf. on Mixed Design of Integrated Circuits and Systems, 2009, pp. 201-204] with the same functions, but whose mixed signal circuitry differs from that proposed in this specification. It is precisely this original circuitry which enables the obtaining of a much lower power consumption than any other hardware previously reported.
The hardware which is the object of this invention is included within the framework of the so-called Winner-Take-All (WTA) or Loser-Take-All (LTA) circuits. These circuits enable the assessment of the highest value—WTA—and lowest value—LTA—in an array of input signals. Said signals may be represented either by voltages or by intensities. Specifically, when applied to the processing of images, the WTA and LTA hardware blocks enable the detection of the local edges of an image; that is, those pixels whose values are the highest—maximum—or the lowest—minimum—with regard to their eight neighbouring pixels.
P201030867-137]. In this approach, the operation is supported by an array of similar processing cells, each managed by the corresponding input signal to be processed. These cells are interconnected by means of a common power source in such a way that a concurrent “competition” arises among all the cells in order to obtain the greatest quantity possible of said power. Ultimately, only one of the cells will remain active, either the winner or the loser, according to the configuration selected.
The other approach is not based on a concurrent interaction of all the signals to be processed, but on a pair processing tree [B. Tomatsopoulos and A. Demosthenous, “Low power, low complexity CMOS multiple-input replicating current comparators and WTA/LTA circuits,” European Conf. on Circuit Theory and Design, 2005, pp. 241-244; H. Hung-Yi, T. Kea-Tiong, T. Zen-Huan, and C. Hsin, “A low-power, high-resolution WTA utilizing translinear-loop pre-amplifier,” Int. Conf. on Neural Networks, 2010]. Thus, the array of signals to be processed is divided into pairs and compared at a first processing level. Only the winners—WTA—or the losers—LTA—reach the next processing level, where comparisons by pairs are performed once again. Ultimately, subsequent to performing the comparison at the final level, the global winner or loser will be obtained.
There also exist a number of hardware structures which may be considered to be hybrid with regard to the above description [R. Dlugosz and T. Talaska, “A low power current-mode binary-tree WTA/LTA circuit for Kohonen neural networks,” Int. Conf. on Mixed Design of Integrated Circuits and Systems, 2009, pp. 201-204].